Rocketsim Speeds Development of Nvidia Kepler and Tegra Processors

June 04,2012

Ramat Gan, Israel (PRWEB) June 04, 2012

Rocketick Technologies Ltd., a pioneer in GPU-based simulation acceleration for chip verification, today announced that its RocketSim™ software has enabled NVIDIA to speed up gate-level simulation of NVIDIA® Kepler™-based GPUs and Tegra® mobile processors.

RocketSim is a GPU-based software solution that seamlessly attaches to existing simulators and accelerates them by more than 10 times, enabling chip manufacturers to reduce time-to-market of new designs by up to 30 percent. Using the latest version of RocketSim, NVIDIA improved the efficiency of its engineering by reducing the simulation and debug time associated with gate-level verification of its giga-gate designs.

“Chip verification requirements are growing exponentially, yet market pressures continue to force chip vendors to shorten their time-to-market, and the challenge is only going to get more difficult,” said Uri Tal, CEO of Rocketick. “RocketSim shortens time-to-market for semiconductor vendors significantly, and gives an incredibly competitive edge to the companies that adopt it.”

The RocketSim simulation acceleration solution works alongside existing customer workflows and environments, requiring minimal ramp-up effort. It can attach to all leading simulators in the market, and its distributed compilation technology, four-state logic support and full visibility capabilities make it a superb tool for the verification of next-generation chip designs.

“RocketSim is reducing our ATPG gate-level simulation time by as much as 10X,” said Jonah Alben, vice president of GPU engineering at NVIDIA. “It is making a big difference in the productivity of the engineers and in the time to complete verification, and we are looking forward to deploying RocketSim more broadly in the future.”

Rocketick is currently working with NVIDIA on plans to expand the use of RocketSim for other gate-level simulations, as well as to deploy GPU-accelerated register transfer level (RTL) simulation workloads to a range of forthcoming processor designs.