Accelerating Time To Market

RocketSim™ helps chip manufacturers reduce the overall time to market of new chip designs by up to 30%. The following diagram illustrates how RocketSim™ can reduce the time to market for the development of a typical ASIC. The assumptions and data are for illustration purposes and may differ significantly on a case-by-case basis.
A typical chip development process involves two major phases: silicon development and silicon revision. The first phase mainly comprises the development, while the second phase focuses on fixing the bugs that were identified as a result of the first phase. The two phases may take altogether approximately two and a half years to complete, including the design, verification and the tape-out processes.
The first silicon revision stage comprises 30% design and 70% verification. The second silicon revision phase comprises only 10% design and 90% verification.
RocketSim™ accelerates the verification process by over 10X. However, since the verification process involves manual processes (for example, the test may stop when a bug is found and then resume after the debug process), we can safely say that it can reduce the verification process by at least 50%. According to the weight of the verification process on the overall process, the entire process is reduced by 30%, reducing the overall time to 1¾ years.
The analysis above is based on the following assumptions:

  • The team involved in the chip development comprises 100 employees.
  • The project duration is 30 months.
  • The overall engineering-year investment is 250.
  • Savings of 30% is equivalent to 75 engineering-years.
  • Assuming the engineer loaded yearly cost is $100K, the total saving is $7.5 million dollars.
  • In addition, the loss of business opportunity is significantly higher and in some cases can reach two orders of magnitude.



  • Reduce overall time to market by up to 30%
  • Reduce verification phase by up to 50%
  • Improve quality by allowing greater coverage of complex designs
  • Save IT costs by enabling software-based acceleration on lower-memory servers