Breaking the Dependency Barrier


Simulator’s Serial Processing
Simulators are event-driven. Due to the complex nature of the designs, with endless dependencies and complex rules, and since most simulators were developed before multi-core processors were available, the common simulators process Verilog code in a single thread, managing a single active queue of events and handling them one at a time. The serial method in which simulators operate means that each run may take a significant amount of time to complete. This cannot be alleviated by adding more computing power as it is not paralleled. In order to accelerate the simulation, a solution that can break the dependency barrier and offer parallel processing of the expressions is needed.  

Rocketick Solves the Parallel Challenge
Rocketick’s patented technology analyzes the Verilog design and maps the dependencies among the expressions into an elaborate dependency graph. It then partitions the dependency graph into many semi-independent threads, each consisting of a series of processing elements. The threads and their processing elements are organized in an efficient manner, allowing optimized continuous parallelization with minimal synchronization among threads. 

Massive Parallel Computing
Rocketick has developed an efficient virtual machine that runs on Nvidia GPUs or Intel XEON CPUs and executes the threads. This unique architecture schedules the threads in a way that utilizes the power and unique nature of multicore processors to accelerate the simulation by over 10X.